62 lines
1.4 KiB
Verilog
62 lines
1.4 KiB
Verilog
/**********************************************************************
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* $my_monitor example -- Verilog HDL test bench.
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*
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* Verilog test bench to test the $my_monitor PLI application.
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*
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* For the book, "The Verilog PLI Handbook" by Stuart Sutherland
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* Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA
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* Contact: www.wkap.il
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* Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
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* Contact: www.sutherland-hdl.com
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*********************************************************************/
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`timescale 1ns / 1ns
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module test;
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reg a, b, ci, clk;
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wire sum, co;
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addbit i1 (a, b, ci, sum, co);
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initial
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$my_monitor(i1);
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initial
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begin
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#0 a = 0;
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#0 b = 0;
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#0 ci = 0;
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#10 a = 1;
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#10 a = 0;
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#10 b = 1;
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#10 a = 1;
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#10 $finish(0);
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end
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endmodule
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/*** A gate level 1 bit adder model ***/
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`timescale 1ns / 1ns
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module addbit (a, b, ci, sum, co);
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input a, b, ci;
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output sum, co;
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wire a, b, ci, sum, co,
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n1, n2, n3;
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/*
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assign n1 = a ^ b;
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assign sum = n1 ^ ci;
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assign n2 = a & b;
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assign n3 = n1 & ci;
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assign co = n2 | n3;
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*/
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// Gate delays are used to ensure the signal changes occur in a
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// defined order.
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xor #1 (n1, a, b);
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and #2 (n2, a, b);
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and #3 (n3, n1, ci);
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xor #4 (sum, n1, ci);
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or #4 (co, n2, n3);
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endmodule
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/*********************************************************************/
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