76 lines
1.5 KiB
Verilog
76 lines
1.5 KiB
Verilog
`timescale 1ns/1ns
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`define DAC_MSB 7
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`define ADC_MSB 15
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`define NSEC 1
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`define USEC (`NSEC*1000)
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`define MSEC (`USEC*1000)
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// TOPLEVEL TO STIMULATE
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module toy_toplevel(
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input wire [`ADC_MSB:0] V_load_adc,
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input wire V_load_valid,
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output reg pwm,
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output reg [`DAC_MSB:0] V_src
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) ;
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parameter time STARTUP_DELAY = 2 * `MSEC;
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parameter real ADC_RANGE = 32.0;
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parameter real ADC_OFFSET = -ADC_RANGE/2.0;
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parameter real DAC_RANGE = 16.0;
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parameter real DAC_OFFSET = -DAC_RANGE/2.0;
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parameter real UPDATE_FREQ_MHZ = 1.0;
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parameter time CLOCK_INTERVAL = `USEC / UPDATE_FREQ_MHZ;
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reg clk = 0;
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reg ls_only = 0;
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real V_load = 0.0;
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function real decode_value( input real base, input real range, input integer msb, input integer value );
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begin
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decode_value = base + range * value / $itor(1<< (msb+1));
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end
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endfunction
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function integer encode_value( input real base, input real range, input integer msb, input real value );
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begin
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encode_value = (value -base) * $itor(1<< (msb+1)) / range;
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end
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endfunction
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always @( posedge(V_load_valid) )
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begin
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V_load = decode_value( ADC_OFFSET, ADC_RANGE, `ADC_MSB, V_load_adc );
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end
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initial
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begin
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clk = 0;
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ls_only = 0;
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#( `USEC * 1 );
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# ( CLOCK_INTERVAL/4 );
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$finish(0); // Stop things for VPI unit test...
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forever
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begin
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# ( CLOCK_INTERVAL/2 );
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clk <= ! clk;
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end
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end
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always @clk
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begin
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ls_only= (V_load >2.5);
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pwm <= clk | ls_only;
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end
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initial
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begin
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V_src = encode_value( DAC_OFFSET, DAC_RANGE, `DAC_MSB, 7.2 );
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end
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endmodule
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