202 lines
2.7 KiB
Verilog
202 lines
2.7 KiB
Verilog
module test;
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// test name collisions
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parameter genblk1 = 0;
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localparam genblk2 = 0;
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typedef reg genblk3;
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reg genblk4;
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wire genblk5;
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event genblk6;
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class genblk7;
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endclass
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function genblk8();
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endfunction;
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task genblk9;
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endtask
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parameter TRUE = 1;
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genvar i;
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genvar j;
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for (i = 0; i < 2; i = i + 1)
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reg r1 = 1;
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for (i = 0; i < 2; i = i + 1)
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for (j = 0; j < 2; j = j + 1)
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reg r2 = 1;
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for (i = 0; i < 2; i = i + 1)
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case (TRUE)
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0: reg r3a = 1;
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1: reg r3b = 1;
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endcase
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for (i = 0; i < 2; i = i + 1)
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if (TRUE)
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reg r4a = 1;
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else
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reg r4b = 1;
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for (i = 0; i < 2; i = i + 1)
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if (!TRUE)
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reg r5a = 1;
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else if (TRUE)
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reg r5b = 1;
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else
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reg r5c = 1;
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for (i = 0; i < 2; i = i + 1)
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if (!TRUE)
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reg r6a = 1;
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else if (!TRUE)
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reg r6b = 1;
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else
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reg r6c = 1;
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case (TRUE)
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0: reg r7a = 1;
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1: reg r7b = 1;
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endcase
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case (TRUE)
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0: case (TRUE)
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0: reg r8a = 1;
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1: reg r8b = 1;
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endcase
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1: case (TRUE)
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0: reg r8c = 1;
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1: reg r8d = 1;
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endcase
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endcase
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case (TRUE)
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0: if (TRUE)
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reg r9a = 1;
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else
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reg r9b = 1;
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1: if (TRUE)
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reg r9c = 1;
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else
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reg r9d = 1;
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endcase
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case (TRUE)
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0: if (!TRUE)
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reg r10a = 1;
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else if (TRUE)
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reg r10b = 1;
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else
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reg r10c = 1;
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1: if (!TRUE)
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reg r10d = 1;
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else if (TRUE)
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reg r10e = 1;
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else
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reg r10f = 1;
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endcase
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case (TRUE)
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0: if (!TRUE)
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reg r11a = 1;
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else if (!TRUE)
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reg r11b = 1;
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else
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reg r11c = 1;
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1: if (!TRUE)
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reg r11d = 1;
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else if (!TRUE)
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reg r11e = 1;
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else
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reg r11f = 1;
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endcase
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if (TRUE)
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reg r12a = 1;
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else
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reg r12b = 1;
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if (!TRUE)
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reg r13a = 1;
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else if (TRUE)
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reg r13b = 1;
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else
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reg r13c = 1;
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if (!TRUE)
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reg r14a = 1;
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else if (!TRUE)
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reg r14b = 1;
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else
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reg r14c = 1;
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if (TRUE)
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if (TRUE)
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reg r15a = 1;
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else
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reg r15b = 1;
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else
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reg r15c = 1;
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if (TRUE)
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if (!TRUE)
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reg r16a = 1;
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else
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reg r16b = 1;
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else
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reg r16c = 1;
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if (TRUE)
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case (TRUE)
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0: reg r17a = 1;
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1: reg r17b = 1;
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endcase
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else
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case (TRUE)
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0: reg r17c = 1;
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1: reg r17d = 1;
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endcase
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if (!TRUE)
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case (TRUE)
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0: reg r18a = 1;
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1: reg r18b = 1;
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endcase
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else if (TRUE)
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case (TRUE)
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0: reg r18c = 1;
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1: reg r18d = 1;
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endcase
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else
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case (TRUE)
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0: reg r18e = 1;
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1: reg r18f = 1;
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endcase
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if (!TRUE)
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case (TRUE)
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0: reg r19a = 1;
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1: reg r19b = 1;
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endcase
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else if (!TRUE)
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case (TRUE)
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0: reg r19c = 1;
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1: reg r19d = 1;
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endcase
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else
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case (TRUE)
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0: reg r19e = 1;
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1: reg r19f = 1;
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endcase
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initial begin
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$list_regs;
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end
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endmodule
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