30 lines
579 B
Verilog
30 lines
579 B
Verilog
module test();
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wire [3:0] IN;
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wire [3:0] OUT;
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assign OUT = IN;
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initial begin
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#1 $peek(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $force(IN[2:1]);
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#1 $peek(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $release(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $force(IN[2:1]);
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#1 $peek(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $poke(IN[2:1]);
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#1 $peek(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $release(IN[2:1]);
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#0 $display("display :%b", OUT);
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#1 $poke(IN[2:1]);
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#1 $peek(IN[2:1]);
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#0 $display("display :%b", OUT);
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end
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endmodule
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