30 lines
531 B
Verilog
30 lines
531 B
Verilog
module test();
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wire [1:0] IN;
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wire [1:0] OUT;
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assign OUT = IN;
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initial begin
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#1 $peek(IN);
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#0 $display("display : %b", OUT);
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#1 $force(IN);
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#1 $peek(IN);
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#0 $display("display : %b", OUT);
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#1 $release(IN);
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#0 $display("display : %b", OUT);
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#1 $force(IN);
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#1 $peek(IN);
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#0 $display("display : %b", OUT);
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#1 $poke(IN);
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#1 $peek(IN);
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#0 $display("display : %b", OUT);
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#1 $release(IN);
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#0 $display("display : %b", OUT);
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#1 $poke(IN);
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#1 $peek(IN);
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#0 $display("display : %b", OUT);
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end
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endmodule
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