luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/ivtest/vpi/final.v

5 lines
80 B
Verilog
Raw Blame History

module tb;
initial $finish(0);
final $display("In final statement.");
endmodule
Reference in New Issue View Git Blame Copy Permalink