83 lines
1.5 KiB
Verilog
83 lines
1.5 KiB
Verilog
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module lvl2;
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reg r;
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time t;
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event e;
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integer i;
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task t_my;
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r = 1'b0;
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endtask
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function f_my;
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input in;
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begin
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f_my = !in;
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end
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endfunction
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initial begin: init
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t_my;
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r = f_my(r);
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r = f_my(i);
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r = f_my(t);
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->e;
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end
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endmodule
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module lvl1;
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lvl2 lvl2();
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endmodule
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module top0;
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reg r;
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time t;
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event e;
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integer i;
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task t_my;
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r = 1'b0;
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endtask
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function f_my;
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input in;
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begin
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f_my = !in;
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end
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endfunction
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initial begin: init
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t_my;
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r = f_my(r);
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r = f_my(i);
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r = f_my(t);
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->e;
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end
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lvl1 lvl1_0();
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lvl1 lvl1_1();
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endmodule
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module top1;
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initial begin: init
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$test;
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end
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endmodule
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