39 lines
862 B
Verilog
39 lines
862 B
Verilog
module top;
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reg [8:1] val;
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wire [1:4] wval;
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reg [3:0] wdrv;
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real r_arr [1:8];
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integer i_arr [8:1];
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integer lp;
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assign wval = wdrv;
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initial begin
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wdrv = 4'b1010;
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for (lp=1; lp<=8; lp=lp+1) begin
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val[lp] = lp % 2;
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r_arr[lp] = lp + 0.25;
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i_arr[lp] = lp - 1;
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end
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#1;
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$check_val(val, 3, 1);
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$check_val(wval, 4, 0);
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$check_val(r_arr, 5, 5.25);
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$check_val(i_arr, 2, 1);
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$display("Original value is %b", val);
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$put_val(val, 2, 1);
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$put_val(val, 1, 0);
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$display(" New value is %b", val);
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$display("Original net value is %b", wval);
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$put_val(wval, 2, 1);
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$put_val(wval, 1, 0);
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$display(" New net value is %b", wval);
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#1;
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// Verify that an update overrides the put value
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wdrv = 4'b1001;
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$display(" net value is now %b", wval);
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end
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endmodule
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