60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
module top();
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reg p_clk, rst_in, reg_req_t;
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wire out;
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weird_ff uut(p_clk, rst_in, reg_req_t, out);
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initial begin
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p_clk = 0;
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rst_in = 1;
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reg_req_t = 0;
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#1;
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rst_in = 0;
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#1;
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p_clk = 1;
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#2;
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p_clk = 0;
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$display("%d", out);
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if (out != 1'bx) begin
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$display("FAILED 1 - ff was reset");
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$finish;
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end
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#1;
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rst_in = 1;
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#1;
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p_clk = 1;
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#1;
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p_clk = 0;
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$display("%d", out);
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if (out != 1'b0) begin
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$display("FAILED 2 - ff was not reset");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // top
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module weird_ff(p_clk, rst_in, reg_req_t, out);
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input p_clk;
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input rst_in;
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input reg_req_t;
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output out;
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reg [1:0] wr_req_pipe;
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parameter G_ASYNC_RESET = 0;
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wire a_rst = (G_ASYNC_RESET != 0) ? rst_in : 1'b0;
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wire s_rst = (G_ASYNC_RESET == 0) ? rst_in : 1'b0;
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always @(posedge p_clk or posedge a_rst)
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if (a_rst | s_rst)
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wr_req_pipe <= 'b0;
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else
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wr_req_pipe <= {wr_req_pipe, reg_req_t};
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assign out = wr_req_pipe[1];
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endmodule // weird_ff
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