73 lines
848 B
Verilog
73 lines
848 B
Verilog
module test (
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Z,
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CO32,
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A,
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B,
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CI);
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input[63:0] A;
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input[63:0] B;
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input CI;
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output[63:0] Z;
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output CO32;
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wire[31:0] Z1;
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wire[31:0] Z2;
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adder32 add0(
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.Z(Z[31:0]),
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.A(A[31:0]),
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.B(B[31:0]),
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.CI(CI));
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carry32 car0(
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.CO (CO32),
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.A (A[31:0]),
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.B (B[31:0]),
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.CI (CI));
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adder32 add1(
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.Z (Z1),
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.A (A[63:32]),
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.B (B[63:32]),
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.CI (1'b0));
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adder32 add2(
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.Z (Z2),
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.A (A[63:32]),
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.B (B[63:32]),
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.CI (1'b1));
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assign Z[63:32] = CO32 ? Z2 : Z1;
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endmodule
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module adder32 (
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Z,
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A,
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B,
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CI);
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input[31:0] A;
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input[31:0] B;
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input CI;
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output [31:0] Z;
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assign Z = A + B + CI;
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endmodule
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module carry32 (
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CO,
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A,
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B,
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CI);
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input[31:0] A;
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input[31:0] B;
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input CI;
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output CO;
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wire[31:0] unused;
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assign {CO, unused} = A + B + CI;
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endmodule
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