58 lines
947 B
Verilog
58 lines
947 B
Verilog
module top();
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wire [7:0] Z, CO;
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reg [7:0] A, B, CI;
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reg ok;
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test test(Z, CO, A, B, CI);
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task check;
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input [7:0] want_z, want_co;
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begin
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$display("A = %d, B = %d, CI = %d", A, B, CI);
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$display("==> Z = %d, CO = %d", Z, CO);
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$display("??? Z = %d, CO = %d", want_z, want_co);
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if (want_co !== CO || want_z !== Z) begin
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$display("FAILED");
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ok = 0;
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end
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$display;
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end
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endtask // check
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initial begin
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ok = 1;
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A = 0;
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B = 0;
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CI = 0;
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#1 check(0, 0);
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A = 4;
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#1 check(4, 0);
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B = 251;
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#1 check(255, 0);
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if (ok)
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$display("PASSED");
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end
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endmodule // top
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module test (Z, CO, A, B, CI);
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parameter width=8;
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input [width-1:0] A, B, CI;
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output [width-1:0] Z, CO;
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reg [width-1:0] Z, CO;
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integer i;
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always @(A or B or CI) begin
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for(i=0; i < width; i=i+1)
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{CO[i],Z[i]} = A[i] + B[i] + CI[i];
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end
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endmodule
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