49 lines
766 B
Verilog
49 lines
766 B
Verilog
module top
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(
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// Outputs
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e, f, g, h,
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// Inputs
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clk, a, b, c, d
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);
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input clk;
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input a, b, c, d;
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output e, f, g, h;
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child child
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(/*AUTOINST*/
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// Outputs
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.e (e),
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.f (f),
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.g (g),
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.h (h),
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// Inputs
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.clk (clk),
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.a (a),
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.b (b),
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.c (c),
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.d (d));
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endmodule // top
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module child(
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// Outputs
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e, f, g, h,
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// Inputs
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clk, a, b, c, d
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);
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input clk;
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input a, b, c, d;
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output e, f, g, h;
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reg e;
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reg f;
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reg g;
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reg h;
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always @ (posedge clk) e <= a;
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always @ (posedge clk) f <= b;
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always @ (posedge clk) g <= c;
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endmodule // child
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