161 lines
3.2 KiB
Verilog
161 lines
3.2 KiB
Verilog
/*----------------------------------------------------------------------
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*
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* module description here
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*
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*---------------------------------------------------------------------*/
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module foo
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(/*AUTOARG*/
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// Outputs
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result_0, result_1,
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// Inputs
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clk, reset, enable_a
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);
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//----------------------------------------
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input clk;
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input reset;
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input enable_a;
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output result_0;
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output result_1;
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//----------------------------------------
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/*----------------------------------------------------------------*/
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/*-AUTOUNUSED-*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*-AUTOREGINPUT-*/
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/*AUTOREG*/
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/*AUTOWIRE*/
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/*------------------------------------------------------------------
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*
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* local definitions and connections.
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*
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* */
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wire enable_0, enable_1;
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assign enable_0 = 1'd1;
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assign enable_1 = enable_a;
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/*------------------------------------------------------------------
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*
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*
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*
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* */
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/* bar AUTO_TEMPLATE (
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.enable (enable_@),
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.result (result_@),
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) */
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bar bar0
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(/*AUTOINST*/
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// Outputs
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.result (result_0), // Templated
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// Inputs
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.clk (clk),
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.enable (enable_0), // Templated
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.reset (reset));
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bar bar1
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(/*AUTOINST*/
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// Outputs
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.result (result_1), // Templated
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// Inputs
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.clk (clk),
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.enable (enable_1), // Templated
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.reset (reset));
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/*----------------------------------------------------------------*/
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endmodule // foo
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// Local Variables:
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// verilog-library-directories:(".")
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// verilog-library-extensions:(".v")
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// End:
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/*----------------------------------------------------------------------
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*
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* module description here
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*
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*---------------------------------------------------------------------*/
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module bar
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(/*AUTOARG*/
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// Outputs
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result,
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// Inputs
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clk, enable, reset
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);
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//----------------------------------------
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input clk;
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input enable;
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input reset;
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output result;
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//----------------------------------------
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/*----------------------------------------------------------------*/
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/*-AUTOUNUSED-*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*-AUTOREGINPUT-*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg result;
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// End of automatics
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/*AUTOWIRE*/
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/*------------------------------------------------------------------
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*
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* local definitions and connections.
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*
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* */
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/*------------------------------------------------------------------
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*
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*
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*
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* */
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always @ (posedge clk) begin
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if (reset) begin
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result <= 1'd0;
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end else begin
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result <= enable;
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end
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end
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/*----------------------------------------------------------------*/
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endmodule // bar
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// Local Variables:
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// verilog-library-directories:(".")
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// verilog-library-extensions:(".v")
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// End:
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