36 lines
623 B
Verilog
36 lines
623 B
Verilog
/*
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* Basics tests of continuous assignment.
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*/
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module testbench();
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reg [3:0] a, b;
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integer c, d;
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wire [3:0] x, y, z;
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assign x = a + b + b;
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assign y = b - a;
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assign z = a + (a * b);
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initial begin
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a <= 4'h2;
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b <= 4'h3;
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#1;
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if (x !== 4'h8)
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begin
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$display("FAILED -- 2 + 3 + 3 !== 8");
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$finish;
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end
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if (y !== 4'h1)
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begin
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$display("FAILED -- 3 - 2 !== 1");
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$finish;
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end
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if (z !== 4'h8)
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begin
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$display("FAILED -- 2 + (2 * 3) !== 8");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // testbench
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