32 lines
724 B
Verilog
32 lines
724 B
Verilog
module test;
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parameter width = 32;
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localparam fill = 32 - width;
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localparam extend = 0;
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reg passed;
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reg [width-1:0] in;
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reg [31:0] lat1, lat2;
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wire sign_bit = in[width-1];
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wire lsb = in[0];
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initial begin
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passed = 1'b1;
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in = 32'h80000001;
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// The following are asserting().
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lat1 <= {{fill{sign_bit}}, in, {extend{lsb}}};
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lat2 = {{fill{sign_bit}}, in, {extend{lsb}}};
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#1;
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if (lat1 !== 32'h80000001) begin
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$display("FAILED: zero-replication (NB): got %h", lat1);
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passed = 1'b0;
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end
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if (lat2 !== 32'h80000001) begin
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$display("FAILED: zero-replication (B): got %h", lat2);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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