70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
/*
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* Copyright (c) 2000 Guy Hutchison (ghutchis@pacbell.net)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module xnor_test;
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reg onebit1, onebit2;
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reg [3:0] small1, small2;
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reg [15:0] large1, large2, large3, large4;
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reg fail;
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initial
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begin
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fail = 0;
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// single bit xnor testing
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if ((1'b0 ~^ 1'b1) === 1'b1) fail = 1;
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if ((1'b1 ^~ 1'b0) === 1'b1) fail = 1;
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if ((1'b0 ^~ 1'b0) === 1'b0) fail = 1;
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if ((1'b1 ~^ 1'b1) === 1'b0) fail = 1;
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// different sized operands (equality)
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for (small1=0; small1 < 15; small1=small1+1)
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begin
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large1 = { 12'b0, small1 };
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large2 = small1 ~^ large1;
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if (large2 !== {16{1'b1}}) fail = 1;
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large2 = large1 ^~ small1;
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if (large2 !== {16{1'b1}}) fail = 1;
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end
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// random test
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// assumes +, &, |, and ~ work correctly
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for (large1 = 0; large1 < 1000; large1=large1+1)
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begin
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large2 = large1 + 1511; // prime number
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large3 = large1 ^~ large2;
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large4 = (large1 & large2) | (~large1 & ~large2);
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if (large3 !== large4)
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begin
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fail = 1;
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$display ("Pattern failed: %h != %h", large3, large4);
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end
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end // for (large1 = 0; large1 < 1000; large1=large1+1)
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if (fail)
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$display ("FAILED");
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else $display ("PASSED");
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$finish;
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end // initial begin
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endmodule // xnor_test
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