76 lines
1.8 KiB
Verilog
76 lines
1.8 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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//
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//
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module main ();
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reg [7:0] array [0:7];
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reg error ;
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reg [3:0] count;
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initial
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begin
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for(count = 0; count <= 7; count = count + 1)
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begin
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array[count] = 1 << count;
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end
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array[2] = 8'bx0z0x0z0;
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$writememb("work/writememb1.dat", array, 6, 1);
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for(count = 0; count <= 7; count = count + 1)
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begin
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array[count] = 'bx;
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end
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error = 0;
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$readmemb("work/writememb1.dat", array);
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for(count = 0; count <= 3; count = count + 1)
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begin
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if(array[count] !== (1<<(6-count)))
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begin
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error = 1;
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$display("FAILED - array[count] == %h, s/b %h",
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array[count], 1 << count);
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end
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end
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if (array[4] != 8'bx0z0x0z0)
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begin
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error = 1;
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$display("FAILED - array[count] == %h, s/b %h",
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array[4], 8'bx0z0x0z0);
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end
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if (array[5] != 8'b00000010)
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begin
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error = 1;
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$display("FAILED - array[count] == %h, s/b %h",
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array[5], 1 << 5);
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end
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if(error == 0)
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$display("PASSED\n");
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$finish ;
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end
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endmodule
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