22 lines
569 B
Verilog
22 lines
569 B
Verilog
module top;
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reg [7:0] array [7:0];
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initial begin
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$writememb();
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$writememb(top);
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$writememb("writemem.txt");
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$writememb("writemem.txt", top);
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$writememb("writemem.txt", array, top);
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$writememb("writemem.txt", array, 0, top);
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$writememb("writemem.txt", array, 0, 7, top);
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$writememh();
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$writememh(top);
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$writememh("writemem.txt");
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$writememh("writemem.txt", top);
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$writememh("writemem.txt", array, top);
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$writememh("writemem.txt", array, 0, top);
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$writememh("writemem.txt", array, 0, 7, top);
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end
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endmodule
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