45 lines
1.4 KiB
VHDL
45 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- The operation is:
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-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received.
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-- 2) An enable allows an internal running counter to count clock pulses
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-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated
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entity TimeBase is
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port(
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CLOCK : in std_logic; -- input clock of 20MHz
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TICK : out std_logic; -- out 1 sec timebase signal
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RESET : in std_logic; -- master reset signal (active high)
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ENABLE : in std_logic;
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COUNT_VALUE: out std_logic_vector (24 downto 0)
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);
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end TimeBase;
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architecture TimeBase_rtl of TimeBase is
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constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second
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signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count
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begin
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RunningCounterProcess : process (CLOCK)
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begin
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if ( CLOCK'event and CLOCK = '1') then
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if (RESET = '1') then
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RunningCounter <= '0' & x"000000";
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elsif ( ENABLE = '1') then
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RunningCounter <= RunningCounter + 1;
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end if;
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else
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RunningCounter <= RunningCounter;
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end if;
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end process;
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TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0';
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COUNT_VALUE <= RunningCounter;
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end TimeBase_rtl;
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