30 lines
432 B
VHDL
30 lines
432 B
VHDL
-- a D-type flip-flop with synchronous reset
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library ieee;
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use ieee.std_logic_1164.all;
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entity fdc is
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port (clk: in std_logic;
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reset: in std_logic;
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d: in std_logic;
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q: out std_logic
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);
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end fdc;
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architecture fdc_rtl of fdc is
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begin
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i_finish: process (clk)
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begin
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if (clk'event and clk = '1') then
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if (reset = '1') then
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q <= '0';
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else
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q <= d;
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end if;
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end if;
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end process;
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end fdc_rtl;
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