35 lines
523 B
Verilog
35 lines
523 B
Verilog
module test;
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reg clk, reset;
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wire [24:0] count;
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initial begin
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clk = 1'b0;
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forever #25 clk = ~clk;
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end
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initial begin
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reset = 1'b0;
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@(negedge clk);
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reset = 1'b1;
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repeat(6) @(negedge clk);
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reset = 1'b0;
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end
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initial begin
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#200000;
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#500;
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if (count != 2000) begin
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$display ("Counting FAILED");
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$finish;
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end
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else begin
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$display ("PASSED");
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#20;
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$finish;
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end
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end
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bigcount duv (.clk(clk), .reset(reset), .count(count) );
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endmodule
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