61 lines
963 B
Verilog
61 lines
963 B
Verilog
`begin_keywords "1364-2005"
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/*
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* This test is from PR#193
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*/
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/* test:tshl
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Compilation fails with vvp from icarus verilog-20010616 snapshot
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$ iverilog -t vvp tshl.v
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ivl: eval_expr.c:418: draw_binary_expr_ls: Assertion `0' failed.
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In vvm, runtime has trouble with $display
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$ iverilog tshl.v
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$ ./a.out
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out=01<some binary characters>
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(looks like the correct output "out=01" followed by some
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random memory garbage.)
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*/
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module tshl;
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reg [2:0] bit;
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wire [7:0] shbit;
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integer i;
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shl shl_0(shbit, bit);
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initial begin
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for(i = 0; i < 8; i = i + 1) begin
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bit <= i[2:0];
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#1
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$display("out=%h", shbit);
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end // for (i = 0; i < 8; i = i + 1)
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$finish(0);
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end // initial begin
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endmodule
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module shl(out, bit);
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output [7:0] out;
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input [2:0] bit;
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reg [7:0] out_reg;
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always @(bit) begin
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out_reg <= 8'h01 << bit;
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end // always @ (bit)
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assign out = out_reg;
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endmodule // shl
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`end_keywords
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