177 lines
3.9 KiB
Verilog
177 lines
3.9 KiB
Verilog
module top;
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reg [1:0] lv, rv;
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reg res, pass;
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initial begin
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pass = 1'b1;
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lv = 2'b00;
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rv = 2'b00;
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res = lv ==? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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rv = 2'b01;
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res = lv ==? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b10;
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rv = 2'b00;
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res = lv ==? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b1x;
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rv = 2'b00;
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res = lv ==? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0x;
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rv = 2'b00;
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res = lv ==? rv;
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if (res !== 1'bx) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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rv = 2'b0x;
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res = lv ==? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b01;
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rv = 2'b0x;
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res = lv ==? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0z;
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rv = 2'b0x;
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res = lv ==? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0x;
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rv = 2'b0x;
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res = lv ==? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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rv = 2'b00;
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res = lv !=? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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rv = 2'b01;
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res = lv !=? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b10;
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rv = 2'b00;
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res = lv !=? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b1x;
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rv = 2'b00;
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res = lv !=? rv;
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if (res !== 1'b1) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0x;
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rv = 2'b00;
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res = lv !=? rv;
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if (res !== 1'bx) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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rv = 2'b0x;
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res = lv !=? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b01;
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rv = 2'b0x;
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res = lv !=? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0z;
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rv = 2'b0x;
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res = lv !=? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b0x;
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rv = 2'b0x;
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res = lv !=? rv;
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if (res !== 1'b0) begin
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$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
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pass = 1'b0;
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end
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// Check in a few other contexts.
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lv = 2'b01;
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rv = 2'b0x;
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res = (lv ==? rv) ? 1'b1 : 1'b0;
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if (res !== 1'b1) begin
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$display("Failed: %b ==? %b (ternary) returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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if (lv !=? rv) begin
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$display("Failed: %b ==? %b (if) returned 1'b%b not 1'b1", lv, rv, res);
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pass = 1'b0;
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end
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lv = 2'b00;
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while (lv ==? rv) lv += 2'b01;
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if (lv !== 2'b10) begin
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$display("Failed: %b ==? %b (while) expected lv to be 2'b10", lv, rv);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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