29 lines
612 B
VHDL
29 lines
612 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity foo_entity is
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port(
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data_i : in std_logic_vector(1 downto 0);
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data_o, data_o2, data_o3 : out std_logic_vector(3 downto 0)
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);
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end foo_entity;
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architecture behaviour of foo_entity is
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begin
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data_o <= "0001" when ( data_i="00" ) else
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"0010" when ( data_i="01" ) else
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"0100" when ( data_i="10" ) else
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"1000";
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-- test cases without the final 'else' statement
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data_o2 <= "0101" when ( data_i="01" );
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data_o3 <= "1100" when ( data_i="10" ) else
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"0011" when ( data_i="01" );
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end behaviour;
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