57 lines
799 B
Verilog
57 lines
799 B
Verilog
/*
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* this test attempts to show a problem with the waits. This skip
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* and skip2 modules should have identical behavior.
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*/
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module skip(r,a);
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input r;
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output a;
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wire r;
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reg a;
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initial
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a=0;
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always begin
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wait(r);
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#1 a=1;
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wait(!r);
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#1 a=0;
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end
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endmodule
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module skip2(r,a);
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input r;
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output a;
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wire r;
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reg a;
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initial
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a=0;
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always @ (r or a) begin
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case ({r,a})
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00: ; // idle
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10: #1 a=1;
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11: ; // idle
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01: #1 a=0;
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endcase
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end
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endmodule
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module test;
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reg r1;
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wire a1;
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reg clk;
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// skip2 skip1(r1,a1); // simulates as expected
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skip skip1(r1,a1); // simulation hangs
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always #50 clk= !clk;
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initial begin
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$monitor($time," ",r1,a1);
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$display("starting");
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#100 r1=0;
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#100 r1=1;
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wait(a1);
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#100 r1=0;
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#1000 $display("timeout"); $finish(0);
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end
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endmodule
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