46 lines
878 B
Verilog
46 lines
878 B
Verilog
module vvp_scalar_value();
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reg [2:0] v1;
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reg [2:0] v2;
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wire [2:0] w1;
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wire [2:0] w2;
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wire [2:0] w3;
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assign ( highz1, strong0) w1 = v1;
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assign (strong1, highz0) w2 = v1;
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assign ( highz1, strong0) w3 = v1;
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assign (strong1, highz0) w3 = v2;
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reg failed;
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initial begin
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failed = 0;
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v1 = 3'bz10; #1;
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$display("%b %v %v %v", w1, w1[2], w1[1], w1[0]);
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if (w1 !== 3'bzz0) failed = 1;
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$display("%b %v %v %v", w2, w2[2], w2[1], w2[0]);
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if (w2 !== 3'bz1z) failed = 1;
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v2 = 3'b000; #1;
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$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
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if (w3 !== 3'bzz0) failed = 1;
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v2 = 3'b111; #1;
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$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
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if (w3 !== 3'b11x) failed = 1;
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v2 = 3'bzzz; #1;
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$display("%b %v %v %v", w3, w3[2], w3[1], w3[0]);
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if (w3 !== 3'bzz0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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