57 lines
1.0 KiB
Verilog
57 lines
1.0 KiB
Verilog
module stimulus (output reg A, B);
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initial begin
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{A, B} = 2'b00;
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#10 {A, B} = 2'b01;
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#10 {A, B} = 2'b10;
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#10 {A, B} = 2'b11;
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end
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endmodule
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module scoreboard (input Y, A, B);
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function truth_table (input a, b);
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reg [1:0] gate_operand;
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reg gate_output;
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begin
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gate_operand[1:0] = {a, b};
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case (gate_operand)
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2'b00: gate_output = 1;
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2'b01: gate_output = 0;
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2'b10: gate_output = 0;
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2'b11: gate_output = 1;
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endcase
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truth_table = gate_output;
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end
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endfunction
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reg Y_t;
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always @(A or B) begin
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Y_t = truth_table (A, B);
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#1;
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//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
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if (Y_t !== Y) begin
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$display("FAILED! - mismatch found for inputs %b and %b in XNOR operation", A, B);
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$finish;
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end
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end
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endmodule
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module test;
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stimulus stim (A, B);
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xnor_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
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scoreboard mon (Y, A, B);
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initial begin
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#100;
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$display("PASSED");
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$finish;
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end
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endmodule
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