49 lines
1.4 KiB
VHDL
49 lines
1.4 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- @author Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for variable initialization.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vhdl_var_init is
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port(init : in std_logic;
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slv : out std_logic_vector(7 downto 0);
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bool : out boolean;
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i : out integer
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);
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end vhdl_var_init;
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architecture test of vhdl_var_init is
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begin
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process(init)
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variable var_slv : std_logic_vector(7 downto 0) := "01000010";
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variable var_bool : boolean := false;
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variable var_int : integer := 42;
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begin
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if rising_edge(init) then
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slv <= var_slv;
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bool <= var_bool;
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i <= var_int;
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end if;
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end process;
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end test;
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