17 lines
310 B
VHDL
17 lines
310 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity udiv23 is
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port (
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a_i : in unsigned (22 downto 0);
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b_i : in unsigned (22 downto 0);
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c_o : out unsigned (22 downto 0)
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);
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end entity udiv23;
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architecture rtl of udiv23 is
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begin
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c_o <= a_i / b_i;
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end architecture rtl;
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