95 lines
1.9 KiB
Verilog
95 lines
1.9 KiB
Verilog
module check (input unsigned [22:0] a, b, c);
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wire unsigned [22:0] int_AB;
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assign int_AB = a / b;
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always @(a, b, int_AB, c) begin
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#1;
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if (int_AB !== c) begin
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$display("ERROR");
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$finish;
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end
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end
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endmodule
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module stimulus (output reg unsigned [22:0] A, B);
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parameter MAX = 1 << 23;
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parameter S = 10000;
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int unsigned i;
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initial begin
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A = 0; B= 1;
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for (i=0; i<S; i=i+1) begin
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#1 A = {$random} % MAX;
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B = {$random} % MAX;
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end
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#1 A = 0;
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B = 1;
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#1 A = 23'h7fffff;
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#1 B = 23'h7fffff;
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#1 B = 1;
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// x and z injected on A
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for (i=0; i<S/2; i=i+1) begin
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#1 A = {$random} % MAX;
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A = xz_inject (A);
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end
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// x and z injected on B
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#1 A = 1;
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for (i=0; i<S/2; i=i+1) begin
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#1 B = {$random} % MAX;
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if (B === 23'b0) B = 1;
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B = xz_inject (B);
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end
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// x and z injected on A, B
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for (i=0; i<S; i=i+1) begin
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#1 A = {$random} % MAX;
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B = {$random} % MAX;
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if (B === 23'b0) B = 1;
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A = xz_inject (A);
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B = xz_inject (B);
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end
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end
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// injects some x, z values on 23 bits arguments
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function [22:0] xz_inject (input unsigned [22:0] value);
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integer i, temp;
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begin
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temp = {$random};
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for (i=0; i<23; i=i+1)
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begin
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if (temp[i] == 1'b1)
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begin
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temp = $random;
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if (temp <= 0)
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value[i] = 1'bx; // 'x noise
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else
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value[i] = 1'bz; // 'z noise
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end
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end
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xz_inject = value;
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end
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endfunction
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endmodule
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module test;
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wire unsigned [22:0] a, b;
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wire unsigned [22:0] r;
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stimulus stim (.A(a), .B(b));
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udiv23 duv (.a_i(a), .b_i(b), .c_o(r) );
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check check (.a(a), .b(b), .c(r) );
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initial begin
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#40000;
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$display("PASSED");
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$finish;
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end
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endmodule
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