74 lines
2.0 KiB
VHDL
74 lines
2.0 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for time related expressions.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.time_pkg.all;
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entity vhdl_time is
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port(a : out std_logic;
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b : in std_logic;
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tout : out time;
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tin : in time);
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end vhdl_time;
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architecture test of vhdl_time is
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signal time_sig : time_subtype := 100 ns;
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begin
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tout <= 140 ns;
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process(b)
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variable time_var : time;
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begin
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if(rising_edge(b)) then
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time_var := 100 ns;
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time_sig := 500 ns;
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a := '0';
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wait for 50 ns;
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a := '1';
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wait for time_sig; -- signal
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a := '0';
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wait for time_const; -- constant
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a := '1';
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wait for time_var; -- variable
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a := '0';
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wait for (time_sig + time_const + time_var);
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a := '1';
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-- Modify variable & signal values
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time_var := 10 ns;
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wait for time_var;
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a := '0';
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time_sig := 20 ns;
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wait for time_sig;
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a := '1';
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-- Test time read from port
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wait for tin;
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a := '0';
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end if;
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end process;
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end test;
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