28 lines
630 B
VHDL
28 lines
630 B
VHDL
--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 27.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity count_ones is
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port ( vec: in std_logic_vector(15 downto 0);
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count : out unsigned(4 downto 0));
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end;
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architecture behaviour of count_ones is
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begin
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process(vec)
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variable result : unsigned(4 downto 0);
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begin
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result := to_unsigned(0, result'length);
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for i in 15 downto 0 loop
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if vec(i) = '1' then
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result := result +1;
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end if;
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end loop;
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count <= result;
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end process;
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end;
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