76 lines
1.5 KiB
Verilog
76 lines
1.5 KiB
Verilog
//
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// Author: Pawel Szostek (pawel.szostek@cern.ch)
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// Date: 01.08.2011
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`timescale 1ns/1ps
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module count_ones_v(input [15:0] vec, output reg [4:0] count);
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integer i;
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integer result;
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always @(vec) begin
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result = 0;
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for (i=15; i>=0; i=i-1) begin
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if(vec[i] == 1'b1) begin
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result = result + 1;
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end
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end
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count = result;
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end
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endmodule
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module check(input [15:0] a, input [4:0] o_vhdl, input [4:0] o_verilog);
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reg ena;
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initial begin
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ena = 0;
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#10;
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ena = 1;
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end
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always @(a)begin
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#1 if (ena == 0) begin end
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else if (o_vhdl !== o_verilog) begin
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$display("ERROR!");
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$display("VERILOG: ", o_verilog);
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$display("VHDL: ", o_vhdl);
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end
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end
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endmodule
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module stimulus (output reg [15:0] a);
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parameter S = 20000;
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int unsigned i,j,k,l;
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initial begin //stimulate data
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for (i=0; i<S; i=i+1) begin
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#5;
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for(k=0; k<16; k=k+1) begin
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a[k] <= inject();
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end
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end
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end
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function inject();
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reg [3:0] temp;
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begin
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temp = $random % 16;
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if(temp >= 10)
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inject = 1'b1;
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else
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inject = 1'b0;
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end
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endfunction
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endmodule
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module main;
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wire [15:0] a;
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wire [4:0] o_vhdl, o_verilog;
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count_ones_v c_vhdl(a,o_vhdl);
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count_ones c_verilog(a,o_verilog);
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stimulus stim(a);
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check c(a,o_vhdl, o_verilog);
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initial begin
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#120000;
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$display("PASSED");
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end
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endmodule
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