23 lines
470 B
VHDL
23 lines
470 B
VHDL
--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 27.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity match_bits is
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port (a,b: in std_logic_vector(7 downto 0);
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matches : out std_logic_vector(7 downto 0)
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);
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end;
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architecture behaviour of match_bits is
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begin
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process(a, b) begin
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for i in 7 downto 0 loop
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matches(i) <= not (a(i) xor b(i));
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end loop;
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end process;
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end;
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