71 lines
1.5 KiB
Verilog
71 lines
1.5 KiB
Verilog
//
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// Author: Pawel Szostek (pawel.szostek@cern.ch)
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// Date: 01.08.2011
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`timescale 1ns/1ps
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module match_bits_v(input [7:0] a,b, output reg [7:0] match);
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integer i;
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wire ab_xor;
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always @(a or b) begin
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for (i=7; i>=0; i=i-1) begin
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match[i] = ~(a[i]^b[i]);
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end
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end
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endmodule
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module check(input [7:0] a,b,o_vhdl, o_verilog);
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always @(a or b) begin
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#1 if (o_vhdl !== o_verilog) begin
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$display("ERROR!");
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$display("VERILOG: ", o_verilog);
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$display("VHDL: ", o_vhdl);
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$finish;
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end
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end
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endmodule
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module stimulus (output reg [7:0] a,b);
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parameter S = 20000;
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int unsigned i,j,k,l;
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initial begin //stimulate data
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for (i=0; i<S; i=i+1) begin
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#5;
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for(k=0; k<8; k=k+1) begin
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a[k] <= inject();
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end
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end
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end
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initial begin //stimulate data
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for (i=0; i<S; i=i+1) begin
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#4;
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for(l=0; l<8; l=l+1) begin
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b[l] <= inject();
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end
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end
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#100 $display("PASSED");
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$finish;
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end
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function inject();
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reg [3:0] temp;
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begin
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temp = $random % 16;
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if(temp >= 10)
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inject = 1'b1;
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else
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inject = 1'b0;
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end
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endfunction
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endmodule
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module main;
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wire [7:0] a,b,o_vhdl, o_verilog;
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match_bits match_vhdl(a,b,o_vhdl);
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match_bits_v match_verilog(a,b,o_verilog);
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stimulus stim(a,b);
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check c(a,b,o_vhdl, o_verilog);
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endmodule
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