23 lines
492 B
VHDL
23 lines
492 B
VHDL
--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 27.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dummy is
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port (o1: out std_logic_vector(7 downto 0);
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o2: out std_logic_vector(7 downto 0);
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o3: out std_logic_vector(7 downto 0)
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);
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end;
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architecture behaviour of dummy is
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begin
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o1 <= (others => '0');
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o2 <= (3 => '1', others => '0');
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o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
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end;
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