26 lines
430 B
Verilog
26 lines
430 B
Verilog
module test;
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wire [7:0] o1, o2, o3;
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dummy foo(.o1(o1), .o2(o2), .o3(o3));
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initial begin
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#1 if (o1 !== 8'h00) begin
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$display("FAILED -- o1 = %b", o1);
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$finish;
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end
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if (o2 !== 8'h08) begin
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$display("FAILED -- o2 = %b", o2);
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$finish;
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end
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if (o3 !== 8'h80) begin
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$display("FAILED == o3 = %b", o3);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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