38 lines
1.1 KiB
VHDL
38 lines
1.1 KiB
VHDL
--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 28.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dummy is
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port (clk : in std_logic;
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input : in std_logic_vector(3 downto 0);
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output : out std_logic_vector(15 downto 0)
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);
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end;
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architecture behaviour of dummy is
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begin
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L: process(clk)
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variable one : integer; -- mix integers and unsigned
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variable a : unsigned (6 downto 0); --
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variable b,c,d : unsigned(6 downto 0);
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begin
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if(clk'event and clk = '1') then
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--do some mess around..
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a(3 downto 0) := unsigned(input);
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a(6 downto 4) := "000";
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one := 1;
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b := a + one; --unsigned plus integer
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b := a + 1; --variable plus constant integer
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c := a + a; --
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c := c - b; --two assignments in a row to the same variable
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d := c + 2;
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output(6 downto 0) <= std_logic_vector(d); --signal assignment
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output(15 downto 7) <= (others => '0');
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end if;
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end process;
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end;
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