26 lines
574 B
VHDL
26 lines
574 B
VHDL
--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 28.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mask is
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port (input : in std_logic_vector(15 downto 0);
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output : out std_logic_vector(15 downto 0)
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);
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end;
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architecture behaviour of mask is
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begin
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L: process(input)
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variable tmp : std_logic_vector(15 downto 0);
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begin
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output <= tmp; --this shouln't really change anything
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tmp := input;
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tmp := tmp and "1010101010101010";
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output <= tmp;
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end process;
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end;
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