20 lines
384 B
Verilog
20 lines
384 B
Verilog
module main;
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wire [15:0] out;
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reg [16:0] in;
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mask dut (.\output (out), .\input (in[15:0]));
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wire [15:0] out_ref = in[15:0] & 16'haaaa;
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initial begin
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for (in = 0 ; in[16] == 0 ; in = in+1)
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#1 if (out !== out_ref) begin
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$display("FAILED: in=%b, out=%b, out_ref=%b", in, out, out_ref);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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