62 lines
1.4 KiB
Verilog
62 lines
1.4 KiB
Verilog
// Copyright (c) 2015 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for selected assignments.
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module vhdl_selected_test;
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logic [1:0] sel;
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logic [3:0] in;
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logic out;
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vhdl_selected dut(sel, in, out);
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initial begin
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in = 4'b1010;
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sel = 1'b00;
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#1;
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if(out !== 1'b0) begin
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$display("FAILED 1");
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$finish();
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end
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sel = 1'b01;
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#1;
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if(out !== 1'b1) begin
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$display("FAILED 2");
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$finish();
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end
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sel = 1'b10;
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#1;
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if(out !== 1'b0) begin
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$display("FAILED 3");
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$finish();
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end
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sel = 1'b11;
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#1;
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if(out !== 1'b1) begin
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$display("FAILED 4");
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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