64 lines
2.1 KiB
VHDL
64 lines
2.1 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Report & assert tests.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.vhdl_report_pkg.all;
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entity vhdl_report is
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port (start_test : in std_logic);
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end vhdl_report;
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architecture test of vhdl_report is
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begin
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process(start_test)
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begin
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if(start_test = '1') then
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-- Report without severity specified, by default it is NOTE
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report "normal report";
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-- Report with severity specified
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-- should continue execution when severity != FAILURE
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report "report with severity"
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severity ERROR;
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-- Assert, no report, no severity specified, by default it is ERROR
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assert false;
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-- Assert with report, no severity specified, by default it is ERROR
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assert 1 = 0
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report "assert with report";
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-- Assert without report, severity specified
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-- should continue execution when severity != FAILURE
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assert 1 = 2
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severity NOTE;
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-- Assert with report and severity specified
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assert false
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report "assert with report & severity"
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severity FAILURE; -- FAILURE causes program to stop
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report "this should never be shown";
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end if;
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end process;
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end architecture test;
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