53 lines
1.6 KiB
Verilog
53 lines
1.6 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Tests initialization of records with aggregate expressions.
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// (based on the vhdl_struct_array test)
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module vhdl_record_elab_test;
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reg [15:0] in;
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wire [15:0] out;
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vhdl_record_elab dut(
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.o_high1(out[15:12]), .o_low1(out[11:8]),
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.o_high0(out[7:4]), .o_low0(out[3:0]),
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.i_high1(in[15:12]), .i_low1(in[11:8]),
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.i_high0(in[7:4]), .i_low0(in[3:0]));
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initial begin
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for (in = 0 ; in < 256 ; in = in+1) begin
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#1 if (in !== out[15:0]) begin
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$display("FAILED -- out=%h, in=%h", out, in);
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$finish;
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end
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end
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if (dut.dword_a[0].low !== 4'b0110 || dut.dword_a[0].high !== 4'b1001 ||
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dut.dword_a[1].low !== 4'b0011 || dut.dword_a[1].high !== 4'b1100)
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begin
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$display("FAILED 2");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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