72 lines
2.3 KiB
VHDL
72 lines
2.3 KiB
VHDL
-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.vhdl_range_pkg.all;
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entity range_entity is
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port (gen_vals: in std_logic);
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end range_entity;
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architecture test of range_entity is
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type int_array is array (integer range <>) of integer;
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signal ascending : int_array(2 to 4);
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signal descending : int_array(9 downto 3);
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signal ascending_rev : int_array(8 to 13);
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signal descending_rev : int_array(15 downto 10);
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signal range_pow : int_array(2**4 downto 0);
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signal range_rem : int_array(8 rem 3 downto 0);
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signal left_asc, right_asc, left_dsc, right_dsc, pow_left, rem_left : integer;
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-- There is no limited ranged integer in SystemVerilog, so just see if it compiles
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signal int_asc : integer_asc;
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signal int_desc : integer_desc;
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begin
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process(gen_vals) begin
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left_asc <= ascending'left;
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right_asc <= ascending'right;
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left_dsc <= descending'left;
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right_dsc <= descending'right;
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pow_left <= range_pow'left;
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rem_left <= range_rem'left;
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-- 'range test
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for i in ascending'range loop
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ascending(i) <= i * 2;
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end loop;
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for i in descending'range loop
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descending(i) <= i * 3;
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end loop;
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-- 'reverse_range test
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for i in ascending_rev'reverse_range loop
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ascending_rev(i) <= i * 4;
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end loop;
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for i in descending_rev'reverse_range loop
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descending_rev(i) <= i * 5;
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end loop;
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end process;
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end test;
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