104 lines
2.8 KiB
Verilog
104 lines
2.8 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
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module range_test;
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range_entity dut();
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initial begin
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int i;
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#1; // wait for signal assignments
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if(dut.left_asc !== 2)
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begin
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$display("FAILED: left_asc should be %2d but is %2d", 2, dut.left_asc);
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$finish();
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end
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if(dut.right_asc !== 4)
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begin
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$display("FAILED: right_asc should be %2d but is %2d", 2, dut.right_asc);
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$finish();
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end
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if(dut.left_dsc !== 9)
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begin
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$display("FAILED: left_dsc should be %2d but is %2d", 2, dut.left_dsc);
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$finish();
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end
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if(dut.right_dsc !== 3)
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begin
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$display("FAILED: right_dsc should be %2d but is %2d", 2, dut.right_dsc);
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$finish();
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end
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if(dut.pow_left !== 16)
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begin
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$display("FAILED: pow_left should be %2d but is %2d", 16, dut.pow_left);
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$finish();
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end
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if(dut.rem_left !== 2)
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begin
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$display("FAILED: rem_left should be %2d but is %2d", 2, dut.rem_left);
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$finish();
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end
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for(i = $left(dut.ascending); i <= $right(dut.ascending); i++)
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begin
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if(2*i !== dut.ascending[i])
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begin
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$display("FAILED: ascending[%2d] should be %2d but is %2d", i, 2*i, dut.ascending[i]);
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$finish();
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end
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end
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for(i = $right(dut.descending); i <= $left(dut.descending); i++)
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begin
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if(3*i !== dut.descending[i])
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begin
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$display("FAILED: descending[%2d] should be %2d but is %2d", i, 3*i, dut.descending[i]);
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$finish();
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end
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end
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for(i = $left(dut.ascending_rev); i <= $right(dut.ascending_rev); i++)
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begin
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if(4*i !== dut.ascending_rev[i])
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begin
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$display("FAILED: ascending_rev[%2d] should be %2d but is %2d", i, 4*i, dut.ascending_rev[i]);
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$finish();
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end
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end
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for(i = $right(dut.descending_rev); i <= $left(dut.descending_rev); i++)
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begin
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if(5*i !== dut.descending_rev[i])
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begin
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$display("FAILED: descending_rev[%2d] should be %2d but is %2d", i, 5*i, dut.descending_rev[i]);
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$finish();
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end
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end
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$display("PASSED");
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end
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endmodule
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