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library ieee;
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use ieee.numeric_bit.all;
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entity rand23 is
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port (
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a_i : in bit_vector (0 to 22);
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b_i : in bit_vector (0 to 22);
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c_o : out bit_vector (0 to 22)
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);
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end entity rand23;
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architecture rtl of rand23 is
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begin
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c_o <= a_i and b_i;
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end architecture rtl;
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