48 lines
807 B
Verilog
48 lines
807 B
Verilog
module check (input unsigned [0:22] a, b, c);
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wire [0:22] int_AB;
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assign int_AB = a & b;
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always @(a, b, int_AB, c) begin
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#1;
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if (int_AB != c) begin
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$display("ERROR");
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$finish;
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end
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end
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endmodule
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module stimulus (output reg unsigned [0:22] A, B);
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parameter MAX = 1 << 23;
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parameter S = 10000;
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int unsigned i;
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initial begin
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A = 0; B= 0;
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for (i=0; i<S; i = i+1) begin
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#1 A = {$random} % MAX;
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B = {$random} % MAX;
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end
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end
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endmodule
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module test;
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wire unsigned [0:22] a, b;
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wire unsigned [0:22] r;
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stimulus stim (.A(a), .B(b));
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rand23 duv (.a_i(a), .b_i(b), .c_o(r) );
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check check (.a(a), .b(b), .c(r) );
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initial begin
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#20000;
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$display("PASSED");
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$finish;
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end
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endmodule
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