45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
// Copyright (c) 2014 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Tests signal initializers.
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module vhdl_init_testbench;
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vhdl_init dut();
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initial begin
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// Simply check if the assigned values are correct
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if (dut.a !== 'b11101001) begin
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$display("FAILED #1: expected 11101001, got %b", dut.a);
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$finish;
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end
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if (dut.b !== 'b1010) begin
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$display("FAILED #2: expected 1010, got %b", dut.b);
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$finish;
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end
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if (dut.c !== 'b1000) begin
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$display("FAILED #3: expected 1000, got %b", dut.c);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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