45 lines
1.6 KiB
VHDL
45 lines
1.6 KiB
VHDL
-- Copyright (c) 2016 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for 'image attribute in VHDL.
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library ieee;
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use ieee.std_logic_1164.all;
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entity image_attr_entity is
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port (start_test : in std_logic);
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end image_attr_entity;
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architecture test of image_attr_entity is
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begin
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process(start_test)
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variable var_int : integer := 10;
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variable var_real : real := 12.34;
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variable var_char : character := 'o';
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variable var_time : time := 10 ns;
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begin
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if(start_test = '1') then
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report "integer'image test: " & integer'image(var_int);
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report "real'image test: " & real'image(var_real);
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report "character'image test: " & character'image(var_char);
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report "time'image test: " & time'image(var_time);
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end if;
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end process;
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end test;
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