51 lines
1.6 KiB
VHDL
51 lines
1.6 KiB
VHDL
-- Copyright (c) 2016 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test file_open() function.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity vhdl_file_open is
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port(active : in std_logic;
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ok : out std_logic);
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end vhdl_file_open;
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architecture test of vhdl_file_open is
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begin
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process(active)
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file ok_file, bad_file : text;
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variable ok_status, bad_status : FILE_OPEN_STATUS;
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begin
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if rising_edge(active) then
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file_open(ok_status, ok_file, "ivltests/vhdl_file_open.vhd", read_mode);
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file_open(bad_status, bad_file, "not_existing_file", read_mode);
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if ok_status = OPEN_OK and bad_status = NAME_ERROR then
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ok := '1';
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else
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ok := '0';
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end if;
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file_close(ok_file);
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end if;
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end process;
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end test;
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